Memory system
This section describes:
The Cortex-A9 processor has separate instruction and data caches. The caches have the following features:
Each cache can be disabled independently. See System Control Register.
Both caches are 4-way set-associative.
The cache line length is eight words.
On a cache miss, critical word first filling of the cache is performed.
You can configure the instruction and data caches independently during implementation to sizes of 16KB, 32KB, or 64KB.
To reduce power consumption, the number of full cache reads is reduced by taking advantage of the sequential nature of many cache operations. If a cache read is sequential to the previous cache read, and the read is within the same cache line, only the data RAM set that was previously read is accessed.
The instruction cache has the following features:
The instruction cache is virtually indexed and physically tagged.
Instruction cache replacement policy is either pseudo round-robin or pseudo random.
The data cache has the following features:
The data cache is physically indexed and physically tagged.
Data cache replacement policy is pseudo random.
Both data cache read misses and write misses are non-blocking with up to four outstanding data cache read misses and up to four outstanding data cache write misses being supported.
05.커널_압축_해제(지현구).pdf
